IEEE计算机体系结构快报 SCIE

期刊简介预计审稿时间： 12周，或约稿

IEEE Computer Architecture Letters is a rigorously peer-reviewed forum for publishing early, high-impact results in the areas of uni- and multiprocessor computer systems, computer architecture, microarchitecture, workload characterization, performance evaluation and simulation techniques, and power-aware computing. Submissions are welcomed on any topic in computer architecture, especially but not limited to: microprocessor and multiprocessor systems, microarchitecture and ILP processors, workload characterization, performance evaluation and simulation techniques, compiler-hardware and operating system-hardware interactions, interconnect architectures, memory and cache systems, power and thermal issues at the architecture level, I/O architectures and techniques, independent validation of previously published results, analysis of unsuccessful techniques, domain-specific processor architectures (e.g., embedded, graphics, network, etc.), real-time and high-availability architectures, reconfigurable systems.

IEEE 计算机体系结构快报是一个经过严格同行评审的论坛，用于发布单处理器和多处理器计算机系统、计算机体系结构、微体系结构、工作负载特性、性能评估和模拟技术以及功耗感知计算等领域的早期高影响力成果。欢迎提交有关计算机体系结构的任何主题的论文，特别是（但不限于）：微处理器和多处理器系统、微体系结构和 ILP 处理器、工作负载特性、性能评估和模拟技术、编译器硬件和操作系统硬件交互、互连体系结构、内存和缓存系统、体系结构级别的功耗和散热问题、I/O 体系结构和技术、对先前发布结果的独立验证、对不成功技术的分析、特定领域的处理器体系结构（例如嵌入式、图形、网络等）、实时和高可用性体系结构、可重构系统。

《Ieee Computer Architecture Letters》(IEEE计算机体系结构快报)编辑部通讯方式为10662 LOS VAQUEROS CIRCLE, PO BOX 3014, LOS ALAMITOS, USA, CA, 90720-1314。如果您需要协助投稿或润稿服务，您可以咨询我们的客服老师。我们专注于期刊投稿服务十年，熟悉发表政策，可为您提供一对一投稿指导，避免您在投稿时频繁碰壁，节省您的宝贵时间，有效提升发表机率，确保SCI检索（检索不了全额退款）。我们视信誉为生命，多方面确保文章安全保密，在任何情况下都不会泄露您的个人信息或稿件内容。